Full synthesized HDL design for All Digital PLL.

Nowadays digital signal processing plays a vital role in communication systems. This paper presents design solution for all-digital PLL (ADPLL) in which all functional blocks have been synthesized from standard digital cells. All subblocks of general top level circuit are described in detail. It is also presents simulation of proposed ADPLL circuit.

digital controlled oscillator, all-digital phase locked loop, digital loop filter, phase detector, standard cell library